MODULE 1

Advanced Digital

Combinational
Circuits – Design and Analysis

Sequential Circuits –
Design and Analysis

Shift Registers and
Counters

Finite State Machine

MODULE 2

Introduction to Linux

Components of UNIX
system

Directory Structure

Utilities and
Commands

Vi Editor

MODULE 3

Static Timing
Analysis

Introduction to STA

Comparison with DTA

Timing Path and
Constraints

Different types
clocks

Clock domain and
Variations

Clock Distribution
Networks

How to fix timing
failure

MODULE 4

Advanced Verilog for
verification

Tasks and Functions

Delays – Regular,
Intra Assignment and Inertial Delays

Race Conditions

File I/O operation

TB Constructs

Self checking
Testbenches

MODULE 5

Code Coverage

Statement coverage

Branch Coverage

Expression Coverage

Path Coverage

Toggle Coverage

FSM – State, Arc and
Sequence coverage

MODULE 6

ASIC Verification
Methodologies

Directed Vs Random

Functional
verification process

Stimulus Generation

Bus function model

Monitors and
reference models

Coverage Driven
Verification

Verification Planning
and management

MODULE 7

[1] Introduction to SystemVerilog

New Data types

Tasks and Functions

Interfaces

Clocking Blocks

[2] Object Oriented Programming and
Randomization

OOP Basics

Classes – Objects and
handles

Polymorphism and
Inheritance

Randomization

Constraints

[3] Threads and Virtual Interfaces

Fork Join

Fork Join_any

Fork Join_none

Event controls

Mailboxes and
semaphores

Virtual Interfaces

Transactors

Building verification
environment

Test cases

[4] Callbacks

Facade Class

Building Reusable
Transactors

Inserting Callbacks

Registering Callbacks

[5] Direct Programming Interface

[6] Functional Coverage

Coverage models

Coverpoints and bins

Cross coverage

Regression testing

MODULE 8

Advanced
SystemVerilog

 

1:Verification Methodology Overview

Lecture 1Introduction to
Verification Methodology

Lecture 2Verification Process

Lecture 3Reusable TB

Lecture 4Verification Environment
Architecture

Lecture 5Constraint Random
Coverage Driven Verification

Lecture 6Verification
Methodologies & Summary

Quiz 1Knowledge Check –
Verification Methodology Overview

2:SystemVerilog Reference Book

Lecture 7SystemVerilog – Quick
Reference Guide

3:SystemVerilog Language Concepts

Lecture 8SV Concepts Agenda

Lecture 9SV Overview

Lecture 10SV Transactions

Lecture 11SV Interface

Lecture 12SV Virtual Interface

Lecture 13SV OOP

Lecture 14SV Randomization &
Functional Coverage

Lecture 15SV TB Architecture

Quiz 2Knowledge Check – SV
Concepts

4:SystemVerilog Datatypes

Lecture 16SystemVerilog
Introduction & Logic Data Type

Lecture 17SV Data Types – 2 State,
Struct & Enum

Lecture 18SV Data Types –
Strings,Packages & Summary

Quiz 3Knowledge Check – Data Types

5:SystemVerilog Memories

Lecture 19SV Memories –
Introduction, Packed and Multi Dimensional Arrays

Lecture 20SV Memories – Dynamic
Arrays & Queues

Lecture 21SV Memories –
Associative Arrays, Array Methods & Summary

Quiz 4Knowledge Check – Memories

6:SystemVerilog Tasks & Functions

Lecture 22SV Tasks & Functions
– Introduction, Void Functions, Fun return & Automatic Task

Lecture 23SV Tasks & Functions
– Pass by value & ref and Summary

Quiz 5Knowledge Check – Tasks
& Functions

7:SystemVerilog Interfaces

Lecture 24SV Interfaces –
Introduction & Verilog ports Vs SV Interface

Lecture 25SV Interfaces – Modports
& Clocking Block

Lecture 26SV Interfaces – Examples
& Summary

Quiz 6Knowledge Check – Interfaces

8:SystemVerilog Object Oriented Programming – Basics

Lecture 27SV OOP – Introduction,
Class Data Type & Objects

Lecture 28SV OOP – Constructor,
Null Object, Object assignments and copy

Lecture 29SV OOP – Shallow Vs Deep
Copy & Summary

Quiz 7Knowledge Check – OOP Basics

9:SystemVerilog Object Oriented Programming – Advanced

Lecture 30SV OOP – Introduction,
Inheritance & Super

Lecture 31SV OOP – Static
properties & methods and Pass by ref

Lecture 32SV OOP – Polymorphism,
$cast, Virtual & Parametrised classes, Summary

Quiz 8Knowledge Check – OOP
Advanced

10:SystemVerilog Randomization

Lecture 33SV Randomization –
Introduction, rand and randc

Lecture 34SV Randomization –
Randomize(), Pre and Post randomize & Constraints

Lecture 35SV Randomization – Set
Membership, Constraints & Summary

Quiz 9Knowledge Check – Randomization

11:SystemVerilog Threads, Mailboxes and Semaphores

Lecture 36SV Threads , Events,
Mailbox and Semaphores

Quiz 10Knowledge Check – Threads
& Mailboxes

12:SystemVerilog Virtual Interface

Lecture 37SV Virtual Interface –
Introduction, Implementation & Examples

Quiz 11Knowledge Check – VIF

13:SystemVerilog Functional Coverage

Lecture 38SV Functional Coverage –
Introduction & CRCDV

Lecture 39SV Functional Coverage –
Covergroup, Coverpoint, Bins, Cross, Methods & Summary

Quiz 12Knowledge Check –
Functional Coverage

14:SystemVerilog Labs

Lecture 40SystemVerilog Lab Manual

Lecture 41Lab 1 Solution : Data
Types

Lecture 42Lab 2 Solution :
Interfaces

Lecture 43Lab 3 Solution : OOP
Basics

Lecture 44Lab 4 Solution :
Advanced OOP

Lecture 45Lab 5 Solution :
Randomization

Lecture 46Lab 6 Solution :
Threads, Mailbox & Semaphores

Lecture 47Lab 7 Solution :
Transaction

Lecture 48Lab 8 Solution :
Transactors

Lecture 49Lab 9 Solution :
Scoreboard & Reference Model

Lecture 50Lab 10 Solution :
Environment & Testcases

15:Case Study 1 : Dual Port RAM – SystemVerilog TB

Lecture 51Verification Plan

Lecture 52Testbench Architecture
and Verification Flow

Lecture 53Transaction and
Generator

Lecture 54Interface and Drivers

Lecture 55Monitors

Lecture 56Scoreboard and Reference
Model

Lecture 57Environment and
Testcases

16:Case Study 2 : Maven SoC – SystemVerilog TB

Lecture 58Maven SoC SystemVerilog
Verification Environment

17:Universal Verification Methodology Overview

Lecture 59Introduction to UVM

Lecture 60UVM Concepts

Lecture 61UVM SoC TB

Lecture 62UVM AHB UVC

Lecture 63UVM SoC TB Examples

Quiz 13Knowledge Check – Universal
Verification Methodology Overview

18:UVM Reference Book

Lecture 64UVM – Quick Reference
Guide

19:UVM TB Architecture and Base Class Hierarchy

Lecture 65UVM Testbench
Architecture

Lecture 66UVM Base Class Hierarchy

Quiz 14Knowledge Check – UVM TB
Architecture and Base Class Hierarchy

20:UVM Factory

Lecture 67UVM Factory – Importance
of using factory

Lecture 68UVM Factory –
Registration Process

Lecture 69UVM Factory – Create
Method and Factory Overriding

Quiz 15Knowledge Check – UVM
Factory

21:UVM – Stimulus Modelling & Testbench Overview

Lecture 70UVM Stimulus Modelling –
Predefined Methods and Field Registration Process

Lecture 71UVM Stimulus Modelling –
Overriding the predefined do_* methods

Lecture 72UVM – TB Overview

Quiz 16Knowledge Check – UVM
Stimulus Modelling & TB Overview

22:UVM Phases & Reporting Mechanism

Lecture 73UVM Phases – Necessity
of Phases & pre-run Phases

Lecture 74UVM Phases – Run Phase,
post-run Phases and Objection Mechanism

Lecture 75UVM Reporting Mechanism

Quiz 17Knowledge Check – UVM
Phases & Reporting Mechanism

23:UVM TLM Ports and Configuration

Lecture 76UVM TLM Ports – Blocking
put and get ports

Lecture 77UVM TLM Ports – TLM FIFO
and Analysis Ports

Lecture 78UVM Configuration –
Introduction to Configuration Facility

Lecture 79UVM Configuration –
Configuration class and Configuration of Virtual Interface

Quiz 18Knowledge Check – UVM TLM
Ports and Configuration

24:UVM – Creating UVM Testbench Components

Lecture 80Creating UVM TB
Components – Sequencers & Drivers

Lecture 81Creating UVM TB
Components – Monitor, Agents, Env and Testcases

Quiz 19Knowledge Check – UVM –
Creating UVM Testbench Components

25:UVM Sequences

Lecture 82UVM Sequences –
Introduction and Sequence item flow

Lecture 83UVM Sequences – Starting
the sequences and Default Sequence

Quiz 20Knowledge Check – UVM
Sequences

26:UVM – Virtual Sequences & Virtual Sequencers

Lecture 84UVM Virtual Sequences
& Virtual Sequencers – Introduction

Lecture 85UVM Virtual Sequences
& Virtual Sequencers – implementation

Quiz 21Knowledge Check – UVM –
Virtual Sequences & Virtual Sequencers

27:UVM Callbacks & Events

Lecture 86UVM Callbacks

Lecture 87UVM Events

Quiz 22Knowledge Check – UVM
Callbacks & Events

28:UVM – Creating Scoreboard

Lecture 88UVM Creating Scoreboard

Quiz 23Knowledge Check – UVM –
Creating Scoreboard

29:UVM – Register Abstraction Layer

Lecture 89UVM RAL – Intro &
Definition of Register Block

Lecture 90UVM RAL – Adapter,
Predictor and Integration

Lecture 91UVM RAL – Definition of
Register Sequences

Quiz 24Knowledge Check – UVM RAL

30:UVM Labs

Lecture 92UVM Lab Manual

Lecture 93Lab1 Solution : Stimulus
Modeling

Lecture 94Lab2 Solution : Factory
Overriding

Lecture 95Lab3 Solution : UVM
Phases

Lecture 96Lab4 Solution : Creating
UVM agent

Lecture 97Lab5 Solution : UVM
Sequences

Lecture 98Lab6 Solution : Virtual
Interface

Lecture 99Lab7 Solution : Agent
Integration

Lecture 100Lab8 Solution : UVM
Scoreboard

Lecture 101Lab9 Solution : SoC –
UVM VE implementation

Lecture 102Lab10 Solution :
Coverage & Regression

31:Final Test

Quiz 25Final Test