Advanced ASIC Verification Training

MODULE 1

Advanced Digital

Combinational
Circuits – Design and Analysis

Sequential Circuits –
Design and Analysis

Shift Registers and
Counters

Finite State Machine

MODULE 2

Introduction to Linux

Components of UNIX
system

Directory Structure

Utilities and
Commands

Vi Editor

MODULE 3

Static Timing
Analysis

Introduction to STA

Comparison with DTA

Timing Path and
Constraints

Different types
clocks

Clock domain and
Variations

Clock Distribution
Networks

How to fix timing
failure

MODULE 4

Advanced Verilog for
verification

Tasks and Functions

Delays – Regular,
Intra Assignment and Inertial Delays

Race Conditions

File I/O operation

TB Constructs

Self checking
Testbenches

MODULE 5

Code Coverage

Statement coverage

Branch Coverage

Expression Coverage

Path Coverage

Toggle Coverage

FSM – State, Arc and
Sequence coverage

MODULE 6

ASIC Verification
Methodologies

Directed Vs Random

Functional
verification process

Stimulus Generation

Bus function model

Monitors and
reference models

Coverage Driven
Verification

Verification Planning
and management

MODULE 7

[1] Introduction to SystemVerilog

New Data types

Tasks and Functions

Interfaces

Clocking Blocks

[2] Object Oriented Programming and
Randomization

OOP Basics

Classes – Objects and
handles

Polymorphism and
Inheritance

Randomization

Constraints

[3] Threads and Virtual Interfaces

Fork Join

Fork Join_any

Fork Join_none

Event controls

Mailboxes and
semaphores

Virtual Interfaces

Transactors

Building verification
environment

Test cases

[4] Callbacks

Facade Class

Building Reusable
Transactors

Inserting Callbacks

Registering Callbacks

[5] Direct Programming Interface

[6] Functional Coverage

Coverage models

Coverpoints and bins

Cross coverage

Regression testing

MODULE 8

Advanced
SystemVerilog